Azure_Bram_225
New member
I was wondering why has AMD not adopted CUDIMM and MRDIMM that Intel is using and that gave them an edge with the memory bandwidth, at least at present.
It looks like they have been working on something better - HB-DIMM.
AMD's HB-DIMM patent
On the surface, it looks similar to MRDIMM approach / place two DDR5 banks and a register/multiplexer on the module and get twice the bandwidth.
But HB-DIMM buffers/registers all lines, so one should be able to have more than one module per channel, without strain on IMC signals - kind of like LRDIMM and more.
Also, HB-DIMM allows for more than two DDR5 banks and/or buffering chips on the module.
And HB-DIMM exposes underlying DDR5 banks and doesn't merge them in RAID-0 principle. So it's up to host how it intends to use them. It can use them as they are and e.g. interlieve them in various ways. This way it can get similar effect as on dual-rank RAMs, only on steroids.
Or it can decide to join channels in (two or more) DDR5 chip groups into 2x size for 2x raw bandwidth but less granularity.
Module form factor is also not a standard DIMM, which milies they might go for something with more signal integrity, like LP/CAMM2 in some way.
I wonder if they intend to use it only on EPYC/TR lines or will it also go into future desktop APUs.
That would sure solve a lot of problems there and enable beefy iGPUs.
Especially on something like AM5 or SP6 successor ( 4 or 6 RAM channels).
It looks like they have been working on something better - HB-DIMM.
AMD's HB-DIMM patent
On the surface, it looks similar to MRDIMM approach / place two DDR5 banks and a register/multiplexer on the module and get twice the bandwidth.
But HB-DIMM buffers/registers all lines, so one should be able to have more than one module per channel, without strain on IMC signals - kind of like LRDIMM and more.
Also, HB-DIMM allows for more than two DDR5 banks and/or buffering chips on the module.
And HB-DIMM exposes underlying DDR5 banks and doesn't merge them in RAID-0 principle. So it's up to host how it intends to use them. It can use them as they are and e.g. interlieve them in various ways. This way it can get similar effect as on dual-rank RAMs, only on steroids.
Or it can decide to join channels in (two or more) DDR5 chip groups into 2x size for 2x raw bandwidth but less granularity.
Module form factor is also not a standard DIMM, which milies they might go for something with more signal integrity, like LP/CAMM2 in some way.
I wonder if they intend to use it only on EPYC/TR lines or will it also go into future desktop APUs.
That would sure solve a lot of problems there and enable beefy iGPUs.
Especially on something like AM5 or SP6 successor ( 4 or 6 RAM channels).
