maverik-sg1
New member
VR ZONE Reports:
Intel expects its forthcoming Conroe and Merom chips to deliver a performance advantage of at least 20 percent over chips from AMD that are slated to be released at the same time. It uses 14 pipeline stages instead of the 31 used by Intel's Pentium 4 processors. The microarchitecture also allows the processor to issue four instructions per clock.
Mav's history lesson - Peple may remember that the reason why Prescott was slower than the Northwood skt478 cpu's was becuase of this 31 stage pipeline - the shorter pipeline is also the reason why Dothan is so quick.
It uses advanced branch prediction technology borrowed from the Pentium 4 designs. Chips built on that microarchitecture will also share the 4MB unified cache. The combination of all those architectural changes will allow Intel to outperform AMD's planned offerings for the second half of 2006 without having to resort to adopting AMD's integrated memory controller design.
Mav's 2p: For those that dont know - unified cahce is where the Intel CPU will share 4MB of caches between two cores (instead oif giving them 2MB per core) - this will help in all sorts of ways (eg multithreeading applications where one core takes on the work requiring all the cache, the other core takes on the calculations)
Instead, Intel will count on its microarchitectural improvements and a faster FSB to deliver the 20 percent improvement in performance over AMD's chips, based on standard benchmarks.
MAV's Final Thoughts - All of a sudden there could be choice to make come the end of 2006 - the seduction of the dark side may be too strong :O I think ultimately the winner will be the best performing SLI/crossfire platform that u can overclock the nuts off.
Intel expects its forthcoming Conroe and Merom chips to deliver a performance advantage of at least 20 percent over chips from AMD that are slated to be released at the same time. It uses 14 pipeline stages instead of the 31 used by Intel's Pentium 4 processors. The microarchitecture also allows the processor to issue four instructions per clock.
Mav's history lesson - Peple may remember that the reason why Prescott was slower than the Northwood skt478 cpu's was becuase of this 31 stage pipeline - the shorter pipeline is also the reason why Dothan is so quick.
It uses advanced branch prediction technology borrowed from the Pentium 4 designs. Chips built on that microarchitecture will also share the 4MB unified cache. The combination of all those architectural changes will allow Intel to outperform AMD's planned offerings for the second half of 2006 without having to resort to adopting AMD's integrated memory controller design.
Mav's 2p: For those that dont know - unified cahce is where the Intel CPU will share 4MB of caches between two cores (instead oif giving them 2MB per core) - this will help in all sorts of ways (eg multithreeading applications where one core takes on the work requiring all the cache, the other core takes on the calculations)
Instead, Intel will count on its microarchitectural improvements and a faster FSB to deliver the 20 percent improvement in performance over AMD's chips, based on standard benchmarks.
MAV's Final Thoughts - All of a sudden there could be choice to make come the end of 2006 - the seduction of the dark side may be too strong :O I think ultimately the winner will be the best performing SLI/crossfire platform that u can overclock the nuts off.
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