AMD Trademarks "Infinity Cache" - Radeon's Rumoured GPU Memory Breakthrough?

[WYP]

AMD Trademarks "Infinity Cache" - Radeon's Rumoured GPU Memory Breakthrough?

AMD Trademarks "Infinity Cache". Are AMD's Infinity Cache rumours legit?



Read more about AMD's rumoured Infinity Cache technology.

 

[KingNosser]

Well it comfirms some of the information going around so that isn't a bad thing, but still doesnt tell us much really. I am looking forward to the up coming events thou

 

[Dicehunter]

It'll probably just be like their HBCC on Vega but able to work with GDDR memory and not just HBM.

 

[AngryGoldfish]

It's exciting to think what AMD could do with something like this when it comes to aggressively pricing their cards as a result of saving GPU space. A 256-bit card with GDDR6 could potentially compete with a 320-bit card using GDDR6X.

 

[NeverBackDown]

Don't forget this could be for APUs and Mobile chips, infinity fabric already exists there, its much less work to manipulate those chips to work together. For a first gen version at least.

Doesn't mean it has to be for desktop RDNA2. Though not saying it can't be.

 

[demonking]

Exciting stuff, I'm interested to see how simple or complex this is,and whether this is a hardware or software change.

 

[WYP]

Based on an AMD patent that I have seen, this could be a method that AMD has developed to create more cache coherency between RDNA 2's CUs, increasing cache effectiveness.

The overly simplistic way of putting it is that RDNA 2 CUs can use interconnected caches to obtain data without using external memory. This method also reduces the need for some data to be written multiple times across several low-level caches on CUs. These changes increase the effective size of low-level caches without increasing cache sizes and could allow GPUs to rely less on external memory, reducing VRAM bandwidth requirements.

If this is AMD's "Infinity Cache" technology, AMD is using an interconnect system (hence "Infinity") to improve RDNA 2's cache structure enough to reduce bandwidth needs. This allows AMD to save due space by using a smaller memory bus and save additional money by creating GPUs with fewer GDDR6 memory chips.

If this hypothesis is in any way accurate, Infinity Cache should allow AMD to meet bandwidth targets with less power consumption and at a lower hardware cost.

https://twitter.com/AlderAzevedo/status/1313279963911553025

Disclaimer, this patent may have nothing to do with Infinity Cache and Infinity Cache may have nothing to do with RDNA 2. Everything is unconfirmed right now.

 

[Kleptobot]

Based on an AMD patent that I have seen, this could be a method that AMD has developed to create more cache coherency between RDNA 2's CUs, increasing cache effectiveness.

The overly simplistic way of putting it is that RDNA 2 CUs can use interconnected caches to obtain data without using external memory. This method also reduces the need for some data to be written multiple times across several low-level caches on CUs. These changes increase the effective size of low-level caches without increasing cache sizes and could allow GPUs to rely less on external memory, reducing VRAM bandwidth requirements.

If this is AMD's "Infinity Cache" technology, AMD is using an interconnect system (hence "Infinity") to improve RDNA 2's cache structure enough to reduce bandwidth needs. This allows AMD to save due space by using a smaller memory bus and save additional money by creating GPUs with fewer GDDR6 memory chips.

If this hypothesis is in any way accurate, Infinity Cache should allow AMD to meet bandwidth targets with less power consumption and at a lower hardware cost.

https://twitter.com/AlderAzevedo/status/1313279963911553025

Disclaimer, this patent may have nothing to do with Infinity Cache and Infinity Cache may have nothing to do with RDNA 2. Everything is unconfirmed right now.

The first thing i thought when you described the sharing of cache space between CU's was that it sounds like a potential side channel for arbitrary code execution

 

[WYP]

The first thing i thought when you described the sharing of cache space between CU's was that it sounds like a potential side channel for arbitrary code execution

I did think that too when I read the patent, but I can't comment on the security of it in any way. I don't have a clue how AMD has or would implement this idea or if it presents any legitimate security concerns. GPUs are stupidly parallel anyway.

 

[AlienALX]

I watched Not An Apple Fan's video last night showing shots of the apparent die.

It's twice the size of the original die. However, he showed shots of the original Navi die and the memory controller was huge. He said to up the bandwidth you would need another, which would make the die massive. I reckon that is why they developed this. It's so they can fit more CUs. It may also lead to them "gluing" dies together in the future, which tbh? I have been expecting at some point for years (hence the scalable thing shown years ago in the graphs).

 

[AngryGoldfish]

I watched Not An Apple Fan's video last night showing shots of the apparent die.

It's twice the size of the original die. However, he showed shots of the original Navi die and the memory controller was huge. He said to up the bandwidth you would need another, which would make the die massive. I reckon that is why they developed this. It's so they can fit more CUs. It may also lead to them "gluing" dies together in the future, which tbh? I have been expecting at some point for years (hence the scalable thing shown years ago in the graphs).

Yeah, we're still waiting for that. RDNA2 does seem to be more "scaleable" than Polaris, Vega, Fiji, and RDNA1 in that they are seemingly able to offer options to all segments of the gaming market. But that's hardly a unique or novel marketing tactic.