Nvidia's working on its own version of AMD's Smart Access Memory tech

So is it known if this is feature of the the PCI-SIG spec is tied to Gen 4? Could be a reason we won't see it on older cards. If it is not, you should take into account the greater bandwidth of Gen 4 would allow more efficient memory access and lessen any overall latency if more than one fetch was needed over a smaller bandwidth.
 
So is it known if this is feature of the the PCI-SIG spec is tied to Gen 4? Could be a reason we won't see it on older cards. If it is not, you should take into account the greater bandwidth of Gen 4 would allow more efficient memory access and lessen any overall latency if more than one fetch was needed over a smaller bandwidth.

From what i can tell the resizable BAR spec came in with PCIe 2.0. Expandable Resizable BAR came in with PCIe 3.0. The change was primarily concerned with how many bits were available to address memory space. Allowing DMA of larger address spaces across PCIe. There was no change to this spec in PCIe 4 at least non that has been published

I'm not sure why this wasn't implemented sooner really. Alternatively they could have chunked the graphics memory before this was a thing and had multiple DMA chunks across the whole or a larger section for the available graphics memory.

I suppose it comes down to, what the low hanging fruit was in terms of time to implement vs performance gain

Edit:
Did some more reading, its to do with addressable memory space in the OS being shared between system memory and GPU memory. 32Bit OSes couldn't support it unless the addressed system memory took a hit, so its only now with the widespread adoption of 64bit that this is feasible.
 
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Like I said before, this needs to be CPU agnostic. Nvidia will make it so because they don't have any CPUs to support; granted don't go out their way to support older CPU generations but make it available to newer ones, both AMD and Intel
 
It did sound like AMDs version was more than just the expandable BAR, making use of their large last level caches on their latest parts for caching the CPU-GPU transfers to improve effective bandwidth and reduce average latency one would assume, but if a good chunk can be gained from making use of the spec alone I assume AMD would need to follow up with that option too now.
 
Like I said before, this needs to be CPU agnostic. Nvidia will make it so because they don't have any CPUs to support; granted don't go out their way to support older CPU generations but make it available to newer ones, both AMD and Intel
They just bought ARM, be prepared for a full Nvidia system.... In 2030 :D
 
I had assumed that AMD got here first because they were able to get around all the security issues by making the system validate the hardware vendor as a direct match between the parts.
I am guessing for this to be implemented both Intel and AMD will have to allow it and add the software support for their own hardware?
 
I had assumed that AMD got here first because they were able to get around all the security issues by making the system validate the hardware vendor as a direct match between the parts.
I am guessing for this to be implemented both Intel and AMD will have to allow it and add the software support for their own hardware?

I don't see the hardware vendor validation being a gaping security hole. Unless people routinely sneak pci devices into systems. From what I can tell it comes down to driver implementation. The pcie spec has the tools, windows has had kernal level support for those tools for years now, amd just implemented the feature first.

I agree that it seems like there might be some secret sauce in their implementation, but that could always be marketing BS. It could very well be an artificial limitation that it only runs on Zen 3 right now, and they'll open it up to more devices later.
 
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