It's not the same as PCIe5 but its design is led by the same engineer and uses the same physical layer, it's a protocol that works over that physical layer. So essentially, it's Intels proprietary version of CCIX. Obviously, this has a lot less industry support than CCIX and rather tellingly has no support from any other hardware vendor at all (unlike CCIX which was developed by AMD, ARM, Huawei, Mellanox Technologies[Now owned by NVidia despite Intels efforts], Qualcomm and Xilinx, all the hardware leaders in the major industries and has several times more support from "customer" companies).
The main difference we know so far is that CXL is a layer on top of PCIe5's physical fabric while CCIX is a layer on top of PCIe4's physical fabric, but by the time we have shipping CXL hardware we will be at generation 3 of the CCIX spec which will likely bring that in line.
So essentially so far this just seems like an attempt by Intel to grab control over an area no one else really wants them to control (Because of their track record regarding "open" standards, See USB1.0/1.1 & USB3.0 at launch or TB3 now, Intels definition of an open standard doesn't actually line up with anyone elses and hardware vendors often have to bully & threaten Intel into actually opening these platforms up properly) and so far they've not indicated much in the way of additional features to lure anyone else meaningful(Hardware vendors who will make the devices that actually use this) in yet.
It's very possible we will only see Intel add-in boards & devices support this interface, though if they keep it similar enough to CCIX the best case scenario is many hardware vendors will support both.