Intel Details their Lakefield Processor Design and Foveros 3D Packaging Tech

I think a lot of companies have been looking into active die stacking for a while but the issue has always been that silicon is a thermal insulator & having stacks of heat producing insulation layers limits the possible power input to each of the layers to tiny levels if you want to sustain it to any degree. I guess they've either found a way to conduct heat better between the layers, or just reduced power use to levels where they have reasonable burst performance and not terrible sustained performance.
 
I think a lot of companies have been looking into active die stacking for a while but the issue has always been that silicon is a thermal insulator & having stacks of heat producing insulation layers limits the possible power input to each of the layers to tiny levels if you want to sustain it to any degree. I guess they've either found a way to conduct heat better between the layers, or just reduced power use to levels where they have reasonable burst performance and not terrible sustained performance.

Yeah. In my eyes that is the reason why this is being used first on a mobile-focused product. Low TDPs and less chance of any thermal problems.
 
Assuming thermals are dealt with, I can very easily see AMD responding to that by replacing the DRAM layer with a up to 32GB HBM layer on their design and retire DRAM for good... Just because they can...

What I don't like here is eventually both companies will end up eating DRAM sticks and placing them inside the CPU, and we'll be stuck with whatever amount of RAM we bought with our CPU. I don't know if this will be ultimately good or bad, I mean it's great performance-wise as RAM will be so close to the CPU but knowing intel, they will probably bundle cheaper CPU's with really low amounts of RAM so that we buy the really expensive CPUs to get RAM...
 
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Assuming thermals are dealt with, I can very easily see AMD responding to that by replacing the DRAM layer with a up to 32GB HBM layer on their design and retire DRAM for good... Just because they can...

What I don't like here is eventually both companies will end up eating DRAM sticks and placing them inside the CPU, and we'll be stuck with whatever amount of RAM we bought with our CPU. I don't know if this will be ultimately good or bad, I mean it's great performance-wise as RAM will be so close to the CPU but knowing intel, they will probably bundle cheaper CPU's with really low amounts of RAM so that we buy the really expensive CPUs to get RAM...

servers will always require more RAM, so I'd imagine that on-die DRAM would act more like a large level 4 cache and have the option for external expansion.

Hmm, if Intel went down that route and had a large CPU L4 DRAM cache, using Optane instead of DDR? would make a lot more sense. Now there's an idea.
 
I think it'll be a long before before the benefits of stacked DRAM on an active die outweighs the thermal limitations enough to warrant putting it on high power chips, Foveros is a step in the direction but the actual interconnects are still quite traditional, so many of the benefits of say TSV stacked memory that you see with HBM don't apply here, it's just to keep the package compact atm.
 
servers will always require more RAM, so I'd imagine that on-die DRAM would act more like a large level 4 cache and have the option for external expansion.

Hmm, if Intel went down that route and had a large CPU L4 DRAM cache, using Optane instead of DDR? would make a lot more sense. Now there's an idea.

Yeah a lot of opportunities to explore with new 2.5D and 3D designs. Should be finally getting more innovative products in the future from Intel
 
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