WYP
News Guru
Need the fastest possible memory for your i9-11900K? G.Skill might have something for you.
Read more about G.Skill's Intel-optimised Z590 memory kits.
Read more about G.Skill's Intel-optimised Z590 memory kits.
G.Skill launches Extreme memory modules for Intel's Z590 platform with up to 5333MHz
- Thread starter WYP
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NeverBackDown
AMD Enthusiast
It's impressive but you mine as well wait for a ddr5 platform as the prices you'll pay for these fast sticks won't be far off from similar ddr5 ones, since they don't need to be as fast in pure clock speed.
looz
Active member
If history is going to repeat itself, it's going to take a while for DDR5 to catch up in de facto latency, despite higher clocks.
But yeah not planning to actually buy these since I got another disappointing memory controller with my 9900k... 8700k was garbage, this is only OK, my best yet is still stuck on a bloody pentium gold. Which managed this: https://valid.x86.fr/v786ts
But yeah not planning to actually buy these since I got another disappointing memory controller with my 9900k... 8700k was garbage, this is only OK, my best yet is still stuck on a bloody pentium gold. Which managed this: https://valid.x86.fr/v786ts
NeverBackDown
AMD Enthusiast
DDR5 offers quite a significant performance improvement clock for clock with higher IPC and overall bandwidth. That's not mentioning the architectural inherently lower latencies. I wouldn't be surprised to see some DDR3 level CAS latencies.
I do fully expect DDR5 to be super expensive just like high end memory is today.
I do fully expect DDR5 to be super expensive just like high end memory is today.
looz
Active member
I can't find anything supporting your claims with DDR5 - in fact, looks to be in line with DDR4 (and subsequently, DDR3) JEDEC:
https://www.anandtech.com/show/16143/insights-into-ddr5-subtimings-and-latencies
Would you mind linking a source? I also don't know what IPC means in relation to memory.
https://www.anandtech.com/show/16143/insights-into-ddr5-subtimings-and-latencies
Would you mind linking a source? I also don't know what IPC means in relation to memory.
NeverBackDown
AMD Enthusiast
Very simple google search, https://www.rambus.com/blogs/get-ready-for-ddr5-dimm-chipsets/
Rambus is a silicone and chip provider, so quite the source. Though the information I stated I learned from one of WYPs past articles.
Rambus is a silicone and chip provider, so quite the source. Though the information I stated I learned from one of WYPs past articles.
NeverBackDown
AMD Enthusiast
Well color me surprised if a new generation of memory is actually better than the old one. Who woulda thunk it?
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NeverBackDown
AMD Enthusiast
The information in the link says otherwise as does multiple other reports from other outlets.
The increased burst length, halving the channel size into 2 smaller ones, both increases efficiency and allows each to concurrently handle fetches. Which decreases overall latency and allows for higher bandwidth at the same clock speed.
This information is not marketing. It's readily available.
The increased burst length, halving the channel size into 2 smaller ones, both increases efficiency and allows each to concurrently handle fetches. Which decreases overall latency and allows for higher bandwidth at the same clock speed.
This information is not marketing. It's readily available.
looz
Active member
Yes, those are great for throughput - but do nothing for single fetch latency. I'm mostly concerned about desktop & gaming performance, which traditionally scale best with latency. It'll be interesting to see what consumer kits can do, but JEDEC spec doesn't show improvements in latency. Even the marketing page only says that they've managed higher capacity without degrading latency. The other claim in their comparison table isn't elaborated further.
But I suppose you're once again ready to continue until eternity, so I'll just wait and see how the performance turns out.
But I suppose you're once again ready to continue until eternity, so I'll just wait and see how the performance turns out.
NeverBackDown
AMD Enthusiast
What I described above gives the CPU the information it needs and less it doesn't. At more frequent intervals. This is lower latency as it gets information sooner and more often into cache, overall less waiting. This is why despite massive increases in speed and bandwidth the latency doesn't spike and the latency overall in real application is essentially lower. As instead of 1 fetch per request it can now do 2 different fetch request which is both faster and easier for the CPU to handle. Which is the important part.
If you are still inclined to not believe me let me put it into perspective.
Using ddr4/5 at 3200mhz is 13.75ns latency, according to the article you gave.
2 fetch request for ddr4 will take 27.5ns
2 fetch request for ddr5 will take 13.75ns latency.
So real world results will show the overall latency within context is lower. It's doing more in the same time for the CPU and that is ultimately lower overall latency.
You're the one who started this debate so ironically if you are tired of it you should not have started it. If you do not like what I post or disagree with and don't want to have a simple conversation then don't say anything at all. You came back with sarcasm and ruined any chance of a simple conversation, it's all on you.
If you are still inclined to not believe me let me put it into perspective.
Using ddr4/5 at 3200mhz is 13.75ns latency, according to the article you gave.
2 fetch request for ddr4 will take 27.5ns
2 fetch request for ddr5 will take 13.75ns latency.
So real world results will show the overall latency within context is lower. It's doing more in the same time for the CPU and that is ultimately lower overall latency.
You're the one who started this debate so ironically if you are tired of it you should not have started it. If you do not like what I post or disagree with and don't want to have a simple conversation then don't say anything at all. You came back with sarcasm and ruined any chance of a simple conversation, it's all on you.
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