AMD to deliver "latency revolution" with Zen 6 Ryzen interconnect tech

[WYP]

AMD's "bridge die" tech could be revolutionary for Zen 6.​

Read more about AMD's Zen 6 latency revolution.

 

[Meaker]

Yeah the I/O die and memory system is holding the core back which is why 3d cache is so effective. If they can do the equivalent of a dual link per ccd cheaper and improve the throughput to the memory then increased clocks and IPC are then available.

 

[NeverBackDown]

Seems logical. Increasing the overall processing capacity per ccd means you need higher memory bandwidth and one way of increasing bandwidth is reduced latency. If they could decrease not just the memory controllers latency but the interconnect from ccd to ccd that would also massively increase IPC.