WYP
News Guru
A lot will change, especially with Genoa.
Read more about AMD's Zen 3 architecture and Zen 4/Genoa plans.
Read more about AMD's Zen 3 architecture and Zen 4/Genoa plans.
AMD reveals early Zen 3/Milan architecture details and Zen 4/Genoa plans
- Thread starter WYP
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NeverBackDown
AMD Enthusiast
This was the natural progression and this is going to be a serious CPU. Working on 7nm+ as well should also help push IPC further.
g0ggles1994
Active member
I'd hazard a guess that Zen 3 will be the last consumer CPU on AM4 as it fits the 'AM4 support until 2020' timeframe. Then Zen 4 will go onto AM5 with DDR5 and PCIe 5.0 after the Zen 4 based EPYC line is launched
WYP
News Guru
Yeah. AMD needs to minimise the downsides of their Zen processor design, and eliminating inter-CCX latencies will be an important step. There will still be inter-die latencies, but giving each CPU core full access to 32+MB of L3 cache is a big deal.
A lot of the reason behind the old "each CCX has four cores" design was due to AMD's restricted budget. It allowed AMD to use quad-core CCX's in mobile and desktop parts without too much redesigning. AMD's original Zen CPUs needed to be cheap to develop over multiple product stacks. Remember that AMD didn't even make a profit back then.
7nm+ will help, but IPC comes from core design changes, not a node shrink. A new node can help with clocks, power and transistor size scaling. The IPC boosts come from core design changes. 7nm+ will be a minor leap from 7nm (when compared from the shift from 14/12nm to 7nm), so Zen 3 will rely on big design changes.
Zen 3 is expected in summer 2020. AM4 compatibility is expected, as Zen 4 should be when AMD moves to DDR5.
This is my guess as well. If Zen 3 Milan can use the same socket as today's EPYC parts, then there is no reason why Zen 3 Ryzen won't get the same treatment.
AMD's next socket will be a push to DDR5, something that actually requires a socket change. Yes, they could make CPUs that support both DDR4 and DDR5, but if we are honest that tactic has never really worked that well in the consumer market. Some Skylake motherboards supported DDR3 IIRC, but I don't think I have seen anyone on this forum using one of those boards.
AlienALX
Well-known member
It was hugely important with Phenom 2 CPUs that supported DDR2 and 3. However things have changed since then and we love throwing things away these days.
I wonder when all of the planet savers are going to realise that e waste is beyond terrible. Course not, 'cause take my money and give me a new phone
I wonder when all of the planet savers are going to realise that e waste is beyond terrible. Course not, 'cause take my money and give me a new phone
NeverBackDown
AMD Enthusiast
Node shrinks can and do bring IPC improvements dude. Why do you think they are often advertised to the public as a performance increase and power efficiency increase? Even Lisa Su made a comment about where those numbers came from about a year ago. AND AMD had a slide promoting Zen 2 IPC improvements and where they came from. Which you also made a report on.
I think you're mixing up single threaded performance and IPC @NeverBackDown, as the slide you've posted shows, the gains from the node shrink is separate from the gains from IPC. While you can rarely get some minute gains from a straight node shrink if it helps reduce cache latencys or similar, usually all the raw performance gains from a node shrink are clock speed/frequency increases, which obviously has no impact on Instructions-Per-Clock by definition.
Generally, all IPC gains has to come from architecture or hierarchy improvements, even if those architectural changes wouldn't have been possible or economical on a larger node they aren't usually attributed to the shrink itself, as the slide you posted demonstrates.
TL: DR: Node shrinks allow you to clock faster and with less power, but IPC is explicitly what happens within a single clock cycle on average and therefore cannot be impacted by clock speed gains.
Generally, all IPC gains has to come from architecture or hierarchy improvements, even if those architectural changes wouldn't have been possible or economical on a larger node they aren't usually attributed to the shrink itself, as the slide you posted demonstrates.
TL: DR: Node shrinks allow you to clock faster and with less power, but IPC is explicitly what happens within a single clock cycle on average and therefore cannot be impacted by clock speed gains.
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NeverBackDown
AMD Enthusiast
IPC and single threaded performance are essentially the same thing. If single threaded performance goes up. So does IPC. If it goes down, so does IPC.
As for node shrink itself, it allows more IPC to be made and allows more transistors on board. Which also further contributes to overall IPC.
I think you also missed where it said "Zen 2 performance contributors" on the slide. 7nm process is listed there as well.
Honestly thought this was common knowledge. I mean even TSMC lists performance metrics for every knew node process.
As for node shrink itself, it allows more IPC to be made and allows more transistors on board. Which also further contributes to overall IPC.
I think you also missed where it said "Zen 2 performance contributors" on the slide. 7nm process is listed there as well.
Honestly thought this was common knowledge. I mean even TSMC lists performance metrics for every knew node process.
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This is not quite true though, you've misunderstood the term. No one has ever disagreed that 7nm contributed to Zen2 performance gains, me and Mark are both pointing out that IPC gains are a very specific type of measurement, that shouldn't be used to indicate performance on its own, and I'm trying to tell you how the term is used by convention in industry(ie it is essentially used as a universal measurement of performance before anything to do with the processing node can impact it, as in IPC is usually measured on a simulator and not the real world as its a value 99% concerned with architecture(and its real world value changes millions of times per second for OoO CISC CPUs). This is why AMD explicitly split the performance gains from IPC(architecture) and design frequency(process node).
IPC is not a measure of end performance or raw performance, and doesn't necessarily have to apply to a single thread either. Instructions-per-Clock is how many instructions are processed per clock. Raising the clock speed cannot raise the instructions processed per clock as I'm sure you can gather. Some architectures trade off IPC for clock speed or vice versa, with Intel Ice Lake, top end single threaded performance is down slightly but IPC is up 25%, because clock speeds are down they've cancelled out any net single threaded performance gain. Conversely raising clock speeds increases single threaded performance while generally decreasing IPC a little past a point as an arch usually can't keep all its pipelines well fed at high clocks.
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g0ggles1994
Active member
Good luck with that dude, these are people who are happy to dish it out, but will not take it in return, even if your arguments are 100% valid. Don't get me started on how many iPhones have been thrown away for the sake of "wanting a new one"It was hugely important with Phenom 2 CPUs that supported DDR2 and 3. However things have changed since then and we love throwing things away these days.
I wonder when all of the planet savers are going to realise that e waste is beyond terrible. Course not, 'cause take my money and give me a new phone
Seems logical, but there's nothing currently tying AMD to a particular RAM architecture. I expect it won't be too hard to have DDR4 and DDR5 I/O dies working with the same CPU chiplets. AMD could feasibly release AM4 Zen 3 and then release AM5 Zen 3 even before Zen 4 is ready.
Actually power efficiency and saving the earth is a big reason why DDR5 parts are unlikely to be able to be designed to accept earlier sticks. Switch to DDR5 unlike previous jumps, the whole power architecture has been changed, VRMs now on the DIMM amongst other things, completely changing motherboard design, I'd says it's super unlikely it'd support older sticks(and if it did motherboards with Ddr4 support too would be more expensive as they need additional VRMs and dual key slots and all that stuff) . I don't think this is an e-waste issue though, just as in many countries the iPhone market is actually mostly 2nd hand, by then the Ddr4 market I'm sure will be a 2nd hand festival too.
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I wouldn't write Intel off. In terms of architecture it has quite a bit to offer. It mostly depends on how well the 10nm process will ramp up. Granted, AMD has been quite lucky in this respect so far.
RobM
Active member
I have not written them off as per the little bit at the end which you did not include in quoting me. As for 10nm, you will find that intel will most likely skip it for mainstream and go straight to 7, seeing as they are still unable to produce 10nm in quantity.
demonking
New member
Yeah no way are intel going to disappear. They are spreading their wings into new areas and thus their resources.
I still half expect Intel to go all Apple on us and create some kind of walled garden with their products. If you want intel you have to get intel CPU, RAM, SSD, Mobo and GPU.
But I could be wrong, It just smells like it and then they can keep selling their products as "elite" or the Ferrari's of computing and taking apple on, though still relying on Microsoft for OS, for now....
Kleptobot
Member
They are sending mixed signals on this front, as they stopped making motherboards but started making ssds and are about to start making gpus
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