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They are using TSMCs SoIC technology, System on Integrated Chip, that they currently showcased at 12 layers maximum. This is as stated obviously what AMDs V Cache is based on and I believe AMD said they won't be going more than 2 layers right now. If they went the full 12 in the future or for say Epyc Scale CPUs, they could add 768MB of cache and for that application, would be completely insane. Intel would have nothing on that.
This is an ingenious move by TSMC to get this technology into existence and an even smarter move on AMDs part to take advantage of it and make it work so well with their chiplet future. They can really take this to the next level in the future. Should really help their IPC gains as we get towards smaller and smaller nodes(and less IPC gains from them).
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