PCI-SIG has finally launched the PCI Express 5.0 Standard

[WYP]

Double the bandwidth of PCI 4.0 with full backwards compatibility.



Read more about PCI-SIG releasing their PCIe 5.0 standard.

 

[Dawelio]

 

[NeverBackDown]

Can basically run 4 2080tis off one x16 slot and still be like oh that's it?

 

[Dawelio]

Can basically run 4 2080tis off one x16 slot and still be like oh that's it?

Now that is just ridicolously insane when you think about it...

 

[HJ1mech]

What would this mean for egpu setups? Would 5.0 basically erase the fps penalty you have because TB3 is only 4 lanes?

 

[NeverBackDown]

What would this mean for egpu setups? Would 5.0 basically erase the fps penalty you have because TB3 is only 4 lanes?

Using TB3 as an example, it would mean a 5.0 specification would provide the same bandwidth using only 1 lane instead of the current 4.

So if they used 2 lanes, it would be double the bandwidth, 3 lanes 3x the bandwidth, etc. Would it erase the penalty? 4.0 might be able to do that, the real issue then becomes latency which neither will solve. Though it isn't all that bad as it is.

I'd expect to see PCIe4.0 implementations first although it shouldn't be around all that long.

 

[grec]

The FPS penalty is not a result of the bandwidth limitations, its the overhead and latency of the Thunderbolt controller. If you ran a GPU from an x4 slot normally there would generally be no performance penalty at all(at least with with mid tier cards at 1080p on most games), but once you have to go via a TB controller you generally get a fairly persistent hit, so it's the controller really where the issue lies, but Intel have started to let people make their own now. Though having more bandwidth would help once you start to move up to higher resolutions as usual.

Personally run my eGPU off a PCIe2.0 x1 Expresscard line though and generally get less of a performance hit than I would using TB3(PCIe3 x4 so 8 times more bandwidth and less performance), but that's an RX460 at 1080p tops.

 

[NeverBackDown]

I've seen conflicting data on the performance issue of lanes vs latency. It's probably a mix of everything.

PCI4.0 is supposed to reduce latency a little bit so if TB4 came out in theory it would inherently be better if only marginally

 

[Bartacus]

Is it just me, or doesn't PCIE4 now feel like a 'stop gap' prior to PCIE5?

 

[NeverBackDown]

Yeah that's basically what happened.

 

[grec]

They were developed concurrently with independent teams, PCIe4 just got delayed heavily while PCIe5 stayed on track. Intel were investing heavily in PCIe5 and most of the work was led by the same engineers from Intel who wrote the USB and Thunderbolt specs.