Yeah early insider reports(From impeccably reliable sources on this topic) are that ~4.1Ghz is the fundamental architectural limit to clock speeds, this happens when you take things so wide that attempting to use higher clock speeds results in too little time between clock pulses for the combinational logic blocks to be ready in time(Have their results in the registers) for the next pulse. (It's worth noting that going wider is almost always more efficient though)
You can get around this problem with node changes specifically if those changes reduce the latency induced by logic gates(On the single digit nanoseconds scale) but they won't be able to get around this issue just from more mature silicon on the same node type. Otherwise you need to modify the arch with more aggressive pipelining(But go too aggressive and you harm efficiency & IPC).
It seems likely Intel will skip Sunny Cove for desktop entirely until Saphire Rapids(Or whatever they end up calling the successive arch) is ready(~2021), it'd probably just get shown up by 14nm comet lake. Sunny Cove is good for laptops or servers(Like 80% of their income tbf), but at best a side step for performance desktop, as the IPC gains will be negated by the clock speed hit.