u cld overlock the silicon components all as standard and the Bus in theory wld b able to handle it (a long as the modulators held up to the new V and can data rates), and im sure these will be implemented in parallel to eliminate ne potetial bottlenecks
In theory these will improve overclockability if there is no limit on the silicon side of the modulators (as the data is optical no more jacking up bus voltages) else view them as a diff bus to OC and apply normal OCing logic