The key part here that will reduce the die size/transistor count cost against NVidia's approach is that they can reuse more of the existing registers & caches, these make up a significant portion of modern processors by area and recent node shrinks have had far less impact here than on the logic side of things. They'll almost certainly still have to increase the size of the existing texture caches to be optimal for raytracing but that would benefit traditional shading techniques to a degree too and it ensures minimal dark silicon during non-hybrid rendering(You're usually looking at a 2:1 ratio at least for cache:logic with raytracing hardware).
Also for anyone who's read the patent, when they refer to "fixed hardware raytracing solutions" they mean units like Imagination Technologies RTU's, you could also say NVidia's approach is hybrid in comparison to past attempts at hardware raytracing units like that, though not quite to this degree.