TBH to me it just looks like they have found a way to make two of the dies on one die/cluster. It may work out cheaper than making separate dies and then having to connect them via the PCB.
I wonder if they changed how the CCx's communicate. Eliminating those, or replacing them with lower-latency ones, might be quite the improvement. It will be interesting to see how this architecture evolves.
TBH to me it just looks like they have found a way to make two of the dies on one die/cluster. It may work out cheaper than making separate dies and then having to connect them via the PCB.
The whole point of connecting several smaller dies together is to reduce cost. Large dies are harder to manufacture and makes errors have a larger impact on yields.
The only difference between this EPYC is how it is arranged and the fact it connects two dies instead of four. There have been no changes to the silicon.
I wonder if they changed how the CCx's communicate. Eliminating those, or replacing them with lower-latency ones, might be quite the improvement. It will be interesting to see how this architecture evolves.
These are the same Summit Ridge dies, though it would be interesting to see how inter-die latencies compare to Threadripper, given the fact that dual-die EPYC Embedded processors are physically closer to each other.
AMD won't change anything major until they start releasing Ryzen 2nd generation and then future architectures. The whole point of their Ryzen chip lineup so far is to use them in several markets.
So far AMD has created Summit Ridge (8-core die over 2 CCXs) and Raven Ridge (4 cores on one CCX with Vega graphics) and they now service their entire Ryzen 3-7, Ryzen Mobile, Threadripper, EPYC and Ryzen/EPYC Embedded markets. This has allowed Ryzen to enter almost every market without AMD needing to design a lot of silicon. Genius move given their small R&D Budget.