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Old 19-11-19, 05:06 PM
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AMD hints at Zen 3's performance gains - Claims its an "entirely new architecture"

AMD is "confident [in] being able to drive significant IPC gains each generation."



Read more about AMD's hint at Zen 3's performance gains.

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Old 19-11-19, 05:25 PM
NeverBackDown NeverBackDown is offline
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AMD will be moving from TSMCs 7nm to TSMCs 7nm+ which itself will give a decent performance improvement. A few percentage better but most of the improvements will be directly from architecture. I'm excited for the combined cache. Might just be what it needs to close the gap in Single threaded performance. Also curious to see if this helps cut down memory latency as well since it will have one central location. Would be interesting if a reviewer could do that if possible.

My only concern is AMD has released Zen twice so far and each time it has required extensive changes to how OS's handle them. By doing this yet again it's just causing more frustration from OS makers and surely HPC groups having to constantly reoptimize for Zen.

AMD is probably leaving performance on the table by doing this. They should be working extremely hard making sure all the changes to each new architecture launch has the best performance possible. Make it easier for everyone and gain the benefits
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Old 19-11-19, 07:40 PM
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Originally Posted by NeverBackDown View Post
AMD will be moving from TSMCs 7nm to TSMCs 7nm+ which itself will give a decent performance improvement. A few percentage better but most of the improvements will be directly from architecture. I'm excited for the combined cache. Might just be what it needs to close the gap in Single threaded performance. Also curious to see if this helps cut down memory latency as well since it will have one central location. Would be interesting if a reviewer could do that if possible.

My only concern is AMD has released Zen twice so far and each time it has required extensive changes to how OS's handle them. By doing this yet again it's just causing more frustration from OS makers and surely HPC groups having to constantly reoptimize for Zen.

AMD is probably leaving performance on the table by doing this. They should be working extremely hard making sure all the changes to each new architecture launch has the best performance possible. Make it easier for everyone and gain the benefits
The radical changes are what's making things work better through, especially with Threadripper. Zen 2 Threadripper and EPYC now look like a single CPU to windows, removing the NUMA issues. Now Threadripper is just a bigger Ryzen, rather than a strange multi-CPU system on a single socket. If anything, the new threadrippers are simpler than the old ones, at least as far as Windows is concerned.

AMD needs to address the downsides of their Zen architecture and that requires some big changes. We haven't had major changes in the CPU market for a long time, so new OS updates to reflect new architectures are just something that we will need to deal with. Look at Intel and Tremont, having a big-little approach to x86. That will need big OS changes too to use correctly. It's just the way things are these days.
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Old 19-11-19, 08:16 PM
NeverBackDown NeverBackDown is offline
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My point is by constantly making it so developers have to constantly reoptimize for the changes just leaves performance on the table as less time is spent getting the most out of it. Just getting it to work is all they have time for.
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Old 19-11-19, 08:25 PM
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Originally Posted by NeverBackDown View Post
My point is by constantly making it so developers have to constantly reoptimize for the changes just leaves performance on the table as less time is spent getting the most out of it. Just getting it to work is all they have time for.
It's a bit of a chicken/egg situation though. We have to dramatically change how we approach CPU's now that we're approaching the limit of silicon. Sure, that can make it more difficult for OS's, but at least it's pushing towards higher performance in the market overall.
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Old 19-11-19, 09:19 PM
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Originally Posted by NeverBackDown View Post
My point is by constantly making it so developers have to constantly reoptimize for the changes just leaves performance on the table as less time is spent getting the most out of it. Just getting it to work is all they have time for.
All of the changes so far have been for the better, software that's optimised for Zen 1 will work great on Zen 2. They are based on the same core architecture. It's just the Zen 2 has fewer weaknesses and new strengths. A lot of the same rules will still apply.

What you're saying only would become a problem if an iteration of Zen was worse than its predecessors in some way. I don't see AMD regressing like that with Zen 3.

By "entirely new architecture", I'm sure AMD's talking about this in an RDNA way. RDNA is still just modified GCN, but it makes big enough changed in enough places to be something that's considered different/new. Software that runs on GCN doesn't run badly on RDNA.
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Old 20-11-19, 07:40 AM
Bagpuss Bagpuss is offline
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Wouldn't those cache changes mean that reliance RAM speeds to get the most out of Ryzen CPUs would be much reduced (eliminated) ?
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Old 20-11-19, 10:15 AM
Giggyolly Giggyolly is offline
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What we really want to see is a big ass L4 cache, like a HBM2 stack chiplet.
But I wouldn't mind chucking in a theoretical 4600x in my build if there's a 15% perf increase over the 3600x.
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Old 20-11-19, 12:46 PM
ET3D ET3D is offline
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Originally Posted by NeverBackDown View Post
I'm excited for the combined cache. Might just be what it needs to close the gap in Single threaded performance. Also curious to see if this helps cut down memory latency as well since it will have one central location.

Larger caches tend to have higher latency. On the other hand, there's a lower chance of a cache miss. I assume that AMD has done its work in this regard, but for pure latency it might not end up faster.
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Old 20-11-19, 02:00 PM
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Larger caches tend to have higher latency. On the other hand, there's a lower chance of a cache miss. I assume that AMD has done its work in this regard, but for pure latency it might not end up faster.
It will be interesting to see how this works. That said, accessing a single, larger cache is probably better overall than assessing a smaller cache and then adding a CCX leap to get access to the extra memory.
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