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Old 19-06-19, 02:28 PM
tgrech tgrech is offline
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Join Date: Jun 2013
Location: UK
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PCI-SIG is a non-profit consortium mostly made up of engineers from a variety of other companies, they work out the spec over a long series of meetings, generally different companies end up having differing levels of influence & investment on each spec, but hardware vendors need to be imminently involved as at least one of them needs to create test silicon to validate the 0.7 spec. Definitely the most time consuming part with PCIe4 was just working out & agreeing on what was possible, which mostly comes from analysis & validation of new techniques for safely increasing signal rate or encoding efficiency. While a combination of two techniques was eventually found that could hit the goal of 16GT/s, there was disagreement on whether the initial plans for PCIe4 would actually be able to achieve those speeds practically in most devices & workloads and so quite a few further refinements had to be made to the 0.7 spec. These are the steps taken in development of a new PCIe spec:

Draft 0.3 (Concept): this release may have few details, but outlines the general approach and goals. For PCIe 4.0 this included the 16 GT/s signaling rate, re-use of the 128/130 encoding scheme developed for PCI 3.0 8 GT/s mode, maintaining full backwards compatibility, etc. and was released in February 2014.
Draft 0.5 (First draft): this release has a complete set of architectural requirements and must fully address the goals set out in the 0.3 draft. The PCIe 4.0 Draft 0.5 specification was released in February 2015.
Draft 0.7 (Complete draft): this release must have a complete set of functional requirements and methods defined, and no new functionality may be added to the specification after this release. Before the release of this draft, electrical specifications must have been validated via test silicon. For PCIe 4.0, two independent implementations were provided to PCI-SIG workgroup members, one from Synopsys, and the other from Mellanox. The PCIe 4.0 Draft 0.7 was released November 15, 2016.
Draft 0.9 (Final draft): this release allows PCI-SIG member companies to perform an internal review for intellectual property, and no functional changes are permitted after this draft.
1.0 (Final release): this is the final and definitive specification, and any changes or enhancements will be through Errata documentation and Engineering Change Notices (ECNs) respectively.
Full article from a Synposys engineer who was heavily involved with PCIe4's practical development: https://www.chipestimate.com/PCI-Exp...cle/2017/02/21
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